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rev. 1.1 11/08 copyright ? 2008 by silicon laboratories si3460-evb si3460-evb si3460 e valuation b oard u ser ? s g uide 1. introduction this document is intended to be used in conjunction with the si3460 data sheet for designers interested in: ? an introduction to power-over-eth ernet (poe) and power sourcing eq uipment (pse) desi gn considerations ? how the si3460 pse controlle r operates in the si346 0-evb reference design ? configuring and operating the si3460-evb 2. overview of the si 3460 and evaluation board the si3460 is a single-port ?48 v power management controller for ieee 802.3af compliant power sourcing equipment (pse). the si34 60 operates directly from a 12 or 15 v isolated input supp ly and integrates a digital pwm-based dc-dc co nverter for generat ing the ?48 v pse output supply. the nega tive polarity on the pse supply provides safety-extra-low-v oltage (selv) compatibility with telephon y ports in the same system. the complete si3460 reference design (i.e., the si3 460-evb) also provides full ieee-complia nt classification and detection as well as a robust disconnect algorithm. intelligent protection circ uitry includes input under -voltage lockout (uvlo), current limiting, and output short-circuit protection. the si3460 is designed to operate completely independe ntly of host processor control. a reset input and an optional led status signal is provided to indicate the port status, including detect, power good and output fault event information for use within the host system. the si3460 is pin programmable to support: ? endpoint and midspan applications, with suppor t for either 10/100base- t or 10/100/1000base-t ? all four classification power levels specified by the ieee 802.3 standard ? classification-based current limiting ? automatic or manual restart after various fault events are detected 3. introduction to poe ieee 802.3-2005 clause 33 (f ormerly ieee 802.3af) is t he standard for providing pow er to a remote ethernet device on the same cable that is carrying data. the powe r is either carried common mode on one of the data pairs (for 10/100/1000base-t) or on the spare pairs for 10/100 base-t only applications. figures 1 and 2 show the possible connections for the po wer. the connections shown in figure 1 should be used for power injection in an ethernet mids pan, and the connections shown in figur e 2 can be used for either midspan or endpoint (switch) applicat ions. designed for use on the pse side for providing pow er to a single ethernet pd port, the si3460 can be configured to operate in either mids pan or endpoint applications. although at this time the existing ieee specification doesn't specifically allow or prohibit gigabit (10/10 0/1000base-t) midspans, in midspan mode, the si3460-evb is desi gned to operate in 10/ 100base-t mode, as the po wer is carried on the spare pairs. however, the si3460 controller can also be designed into gigabit endpoints with the power connected to either the data or spare pairs.
si3460-evb 2 rev. 1.1 figure 1. power carried over the spare pair (10/100base-t applications only) note: this is the connection scheme implemented on the si3460-evb reference design. figure 2. power carried over the signal (data) pair power sourcing equipment (pse) powered device (pd) 48 v + _ tx rx 4 5 1 2 3 6 7 8 spare pair signal pair signal pair spare pair 4 5 1 2 3 6 7 8 rx tx pd i/f and dc-dc converter power sourcing equipment (pse) powered device (pd) 48 v tx rx 4 5 1 2 3 6 7 8 spare pair signal pair signal pair spare pair 4 5 1 2 3 6 7 8 rx tx dc-dc converter and pd i/f
si3460-evb rev. 1.1 3 4. pse detection, classificatio n, power-up, and power removal the basic sequence for applying power is shown in figure 3. following is a description of the functions that must be performed in each phase. figure 3. detection, classification, powerup, and disconnect sequence 4.1. detection during the detection phase, the pse probes with limit ed current and voltage to determine if a 25 k ? signature is present. a valid pd must present between 23.75 and 26.25 k ? in the range of 2.7 to 10.1 v, with an offset (due to the bridge diodes) of up to 1.9 v, an d a parallel capacitance of between 0. 05 and 0.12 f. an ieee-compliant pse probes 2.8 and 10 v, with at least a 1 v step and current limit of <5 ma. th e pse must accept signatures in the range of 19?26.5 k ? with capacitance of up to 0.15 f and must reject resistance <15 k ? or >33 k ? as well as capacitive signatures >10 f. the strict limits on the detection phase ensure that n on poe enabled devices are not inadvertently powered. for endpoint applications, detection must be completed withi n 500 ms of applying a valid signature. when configured as a midspan there is a possibility that the pse circuit will compete with an endpoint pse, and, as required by the ieee specifications, the si3460 is therefore required to wait at least 2 seconds afte r an unsuccessful detection cycle to repeat the detection process. voltage classification detection apply power turn off time 2.8 v 10 v 15.5 v 44 v 57 v 20.5 v
si3460-evb 4 rev. 1.1 4.2. classification classification is optional and is performed by applyi ng between 15.5 and 20.5 v to the pd and measuring the current. the maximum power level that can be drawn by the pd is determined according the following table. currents not falling in these ranges maybe be tr eated as the higher or lower classification level. currents above 45 ma may be treated as class level 0 or 4, which is 15.4 w in either case. 4.3. power-up after the optional classification step, power is applied. per the ieee specific ation, the pse must supply between 44 and 57 v to the pd. for longer durations above 50 ms th e power may be removed if the maximum power level of either 4, 7, or 15.4 w is exceeded. if the current e xceeds 400 ma, the power must be removed in 75 ms. for short-circuit protection, output power is removed immediat ely if the output current exceeds 800 ma or the output voltage drops below 30 v. if power is removed due to an overload condition, detection must not be attempted again for at least 2 s. 4.4. disconnect (power removal) the si3460 supports a robust disconnect algorithm to av oid false disconnection. removal of a pd can be sensed by determining that the dc current is less than 5 ma for between 300 and 400 ms. if the current then exceeds 10 ma for at least 60 ms, the power must not be removed, and the 300?400 ms timer restarts. table 1. classification levels classification level minimum pse power level current measured class 0 15.4 w <5 ma class 1 4 w 8?13 ma class 2 7 w 16?21 ma class 3 15.4 w 25?31 ma class 4 15.4 w 35?45 ma
si3460-evb rev. 1.1 5 5. the si3460 pse controller in addition to providing a complete dc-dc controller to generate the pse output supply, the si3460 is a fully ieee compliant pse power management controller. the si3460 is specifically designed and co nfigured to work with an applications circuit (si3460-evb) that together implement a si ngle port pse solution for either midspans or endpoints. referring to the detailed evaluation board schematics in section ?8. si3460-evb schematics and pcb layout?, the overall functionality is described for each operating state of the si3460 as follows: 5.1. initialization and op erating mode configuration the si3460 is initialized at power up, or whenever pin 8 (rst ) is held low and then allowed to transition high. upon reset (rst asserted), the voltage at the status pin (as de termined by resistors r28 and r30) is sensed to determine the operating mode of the si3460. the dete ction process begins immediately after initialization. any combination of the following three operating modes can be set by the r28 and r30 resistor pair, as indicated below: ? classification level: sets what maxi mum power level the si3460 will support. ? endpoint or midspan mode: controls the ba ckoff timing per the ieee specifications. ? restart action on fault or overload: determines whethe r or not the si3460 will automa tically restart after 2 s when a fault or overload condition (e.g., input uvlo, out put short-circuit event, cl assification power level exceeded) is detected, or wait to restart until the rst pin is asserted. table 2. operating modes nominal status pin voltage operating mode r28, r30 power level supported (w) classes supported endpoint/ midspan restart action on fault or overload event pin voltage at vee 2 k ? , np 15.4 all class levels endpoint auto restart after 2 s 3.0 v 2.21 k ? , 22.1 k ? 7.0 class 1 or 2 2.75 v 2.37 k ? , 11.8 k ? 4.0 class 1 2.5 v 2.61 k ? , 8.06 k ? 15.4 all class levels restart on rst low or when open circuit detected 2.25 v 2.94 k ? , 6.19 k ? 7.0 class 1 or 2 2.0 v 3.32 k ? , 4.99 k ? 4.0 class 1 1.75 v 3.83 k ? , 4.22 k ? 4.0 class 1 midspan restart on rst low or when open circuit detected 1.5 v 4.42 k ? , 3.57 k ? 7.0 class 1 or 2 1.25 v 5.36 k ? , 3.16 k ? 15.4 all class levels 1.0 v 6.81 k ? , 2.80 k ? 4.0 class 1 auto restart after 2 s 0.5 v 14 k ? , 2.26 k ? 7.0 class 1 or 2 < 0.25 v np, 2 k ? 15.4 all class levels
si3460-evb 6 rev. 1.1 5.2. ctrl1 and ctrl2 these two pins are the output of two 96 khz 8-bit pulse width modulato rs. the output of these pins is averaged using r15, r29, and c5 to produce a dc level across c5 that is controllable with 16-bit resolution. this dc voltage is used to control both the detection process and the pulse width modulator for the dc-dc converter. 5.3. detection during the detection phase, the pass transistor m2 is hel d off by driving the gate pin high. the 250 khz clock for the pwm circuit is held low, forcing the switcher fet m1 off. in the detect state, the output volta ge is determined by the output of u18a feeding the resistive bridge r1, r2, and r3. the pd at the other end of a cable forms the fourth leg of the bridge. the return path to vee is through d8 and l1. the bridge null is read through amplifier u18b, which is fed to the si3460 pin deta. the output of u18a is contro lled by the ctrl1 and ctrl2 pins as noted earlier. for most of the detection cycle, the ctrl pins are held high which forces u18a low, pr oducing no output. the bridge voltage is varied to force ieee compliant detection volt ages of approximately 4.5 and 7.5 v across the bridge with 20 ms delay and robust three-point detection algorithm at 4.5, 7.5, and back to 4.5 v. to robustly insure that the pd has a valid resistive signature, the bridge null is checked as the voltage in creases and then checked again as the voltage decreases. relevant waveforms are shown in figure 4 and figure 5 on page 11. 5.4. pwm in order to apply power to the load, m2 is turned on by driving the si3460's gate pin high. at the same time, the pwm circuitry is enabled by turning on the 250 khz clo ck (250 khz pin). the 250 khz square wave is converted to a triangular shape by the filter r14 and c6. the dc le vel set by ctrl1 and ctrl2 is used to control the pwm comparator u19b that drives the switcher fet through gate driver u3. the output voltage is sensed through resistor divider r43 and r44, and th e output current is sensed through resistor r4. the si3460 integrates an a/d that measures these quantities and varies the ctrl1 and ctrl2 duty cycle to regulate the output current and voltage as desired. 5.5. classification for classification, m2 is turned on and the pwm is enable d. the si3460 is programmed to perform classification at 18 v output voltage, with a current limit of between 50 an d 100 ma. classification is performed after allowing 20 ms of settling time. since the si3460-evb is designed for a single port pse app lication, the classification information is only used to determine if the load is in the range t hat is supported, according to the mode of the si3460 determined at power up (refer to status pin in section ?5.1. init ialization and operating mode configuration?). if the measured classification level is not in the support ed range, an error is declared and the si 3460 will either time out and retry and wait for a reset as determined by the power up mode of operation. relevant waveforms are shown in figure 5 on page 11 and figure 6 on page 12. if the class level is in the supported range, the si3460 proceeds to powerup. table 3. classification levels classification mode pse minimum output power action performed o verload current threshold i cut (max) overload current limit i lim (max) full power 15.4 w always apply full power 400 ma 450 ma class 1 only 4 w only apply power if the current is between 8 and 13 ma (class 1) 98 ma 450 ma class 1 or class 2 7 w only apply full power if the current is between 8 and 21 ma (class 1 or class 2) 180 ma 450 ma
si3460-evb rev. 1.1 7 5.6. power-up after successful classification, the si3460 is configured to produce a nominal ?50 v output voltage. the overload current limits are set based on the cla ssification voltage on the status pin at powerup. refer to table 1 of the si3460 data sheet fo r more information. for output current durations lasting longer than 60 ms, t he power is removed if the maximum power level of either 4, 7, or 15.4 w is exceeded by approxim ately 10%, as determined by the oper ating mode detected at start up (refer to section ?5.1. initialization and operat ing mode configuration?). in the event of an output short circuit, the si3460 will immediately disconnect so as to prevent sh orting the input supply through d8 and l1. the si3460 can be configured to operate in a mode where it will automatically retry de tection and power up after an overload. alternatively, the si3460 can be programmed to si gnal an error condition has occurred, in which case the user must assert rst (e.g., by pushing the reset switch on the si 3460-evb) to start a new detection and power up cycle. as set by the initial voltage on the status pin at power up, the si3460 will then automa tically resume the detection process for "automatic restart configuration" unless the si3460 is conf igured in a "restart after a reset condition" mode and a fault conditi on is detected; in that ca se, the led will flash rapidly, and the detection process will automatically start again afte r 2.2 seconds. power will not be provided unti l an open-circuit c ondition is detected. once the si3460-evb de tects an open-circuit condit ion (normally by removing t he ethernet ca ble from the si3460-evb?s rj-45 jack labelled ?to pd?) , the detection process begins, the st atus led blinks at the rate of 3 times per second, and the si3460 is then allowed to go into classification and powerup m ode if a valid pd signature resistance is detected. the relevant wave form is shown in figure 6 on page 12. 5.7. disconnect (power removal) the si3460 supports a robust disconn ect algorithm. if the current drops below 5 ma for between 300 and 400 ms, the power is removed. if the output current then exceeds 10 ma for at least 60 ms, the power is not removed. the si3460 will continue to provide power un less a disconnect or overload conditio n is sensed. the only other way to force the si3460 to disconnect power is by doing a reset. the relevant waveform is shown in figure 7 on page 12. 5.8. current limit control the si3460's overcurrent trip point is determined by the output power set during the classification stage power granting process. if the output current exceeds the threshold, a timer counts up towards a time-out of 60 ms. if the current drops below the set threshold, the timer counts down towards zero at 1/16th the rate. if the timer reaches 60 ms, an overcurrent fault is declared, and the channel is shut down by turning off th e dc-dc converter clock and then turning off the fet m1. after an overcurrent fault event, the led will flash rapidly. as set by the initial voltage on the status pin at power up, the si3460 will then automa tically resume the detection process for "automatic restart configuration" unless the si3460 is conf igured in a "restart after a reset condition" mode and a fault conditi on is detected; in that ca se, the led will flash rapidly, and the detection process will automatically start again afte r 2.2 seconds. power will not be provided unti l an open-circuit c ondition is detected. once the si3460-evb de tects an open-circuit condit ion (normally by removing t he ethernet ca ble from the si3460-evb?s rj-45 jack labelled ?to pd?) , the detection process begins, the st atus led blinks at the rate of 3 times per second, and the si3460 is then allowed to go into classification and powerup m ode if a valid pd signature resistance is detected. 5.9. uvlo the si3460-evb referenc e design is optimized for 12 to 15 v nomi nal input voltages* (11 v minimum to 16 v maximum). if the input voltage drops below 10 v in detection mode or if the output voltage drops below 10 v in classification or power up mode, a uv lo condition is declared which genera tes the error condition (led flashing rapidly). an under-voltage event is a fault condition which is reported through the status led as a rapid blinking of 10 flashes per second. the uvlo condition is continuously monitored in all operating states. *note: some mosfet gate drivers operate at a maximum supply vo ltage of 14 v (for example, tps2828). in that case, the input voltage must be limited to a maximum of 12 v.
si3460-evb 8 rev. 1.1 5.10. status led function during the normal detection sequence, the status led flashes at approximately 3 times per second as the detection process continues. after successful power up, the led glows continuously. if there is an error condition (i.e., class level is beyond programmed value, or a fault or over current condition has been detected), the led flashes rapidly at 10 times per second). this occurs for two seconds for normal error delay and, in the case of the "restart after a reset condit ion," the led will flash rapidly, and the dete ction process will auto matically start again after 2.2 s and power will not be provided until an open circuit condition is detected. once the si3460-evb detects an open circuit condition, the led blinks at 3 times per second. if the powered device (pd) is disconnected so that a di sconnect event occurs, the led will start flashing at 3 times per second once the detect process resumes.
si3460-evb rev. 1.1 9 6. design and layout considerations 6.1. general recommendations the si3460-evb schematic and layout are intended to be used as a reference for all customer designs. the si3460-evb has been tested by the university of new ha mpshire intero perability lab (unh iol) to comply with the relevant ieee 802.3 clause 33 specifications. unh test reports can be download ed from www.silabs.com/poe. since the si3460?s performance in an application depends on external components and pcb layout, customers are ultimately responsible for validating their design?s conformance to all relevant industry, safety, and customer-specific requirements. for applicat ions support, contact poeinfo@silabs.com. 6.2. isolation the ieee 802.3 specification re quires the pse output power to be isolated from earth ground*. to accomplish this, the input power source must be isolated from earth gro und. also, do not connect the si3460's ground connection (pin #11) to earth ground, as this pin serves a circuit reference point only in the si3460-evb. *note: if the input power supply is referenced to earth ground, and if one of the output pads is connected to ground, it can create a high-current fault condit ion that will not be protected. 6.3. selv-compliant output voltage since the output of the si34 60-evb reference design is designed to be less than 57 vdc under all co nditions, it is considered a selv circuit. the si3460-evb is designed to produce a negative output voltage with res pect to the input voltage. the reason this is done is because the si3460 will often be used in applications and en vironments where a standard telephone circuit or slic, such as t he si3210/15/32 /33, will be powered fr om the same 12 to 15 v isolated input power supply. conventionally, these circuits produce large n egative operating vo ltages. since the si 3460-evb reference design is also designed to produce negative voltages, the si3460-evb implementation eliminates the possibility of a hazardous voltage difference between a slic output and the si3460-evb's pse output. 6.4. surge protection the si3460-evb applicati ons design includes a clamp diode, d12, to protect against the 50 sec intra-building lightening surges, as spec ified in ieee 802.3. additional protection, such as a 1 a fuse in the output circuit, may be required for applications in which the ethernet cab ling is not intra-building. 6.5. emi and emc the si3460-evb applications solution is designed to be compliant with fcc class b (cispr22) for radiated emissions, as well as fcc part 15 (en55022) for cond ucted emissions. the pcb layo ut of the si3460-evb should be closely followed to prevent emi and emc issues. the keys to robust emi and emc performance are: ? keep the current loops in the switcher circuit small-diameter. ? lay out the current loop when the fet is on similarly to the current loop when the fet is off. ? connect filter caps to the power circuitry and not to reference planes. ? for better emi performance, use shielded inductors for l1 and l4. 6.6. thermal considerations inductor l1: for improved thermal performanc e, silicon laboratories strongly recommends using a shielded inductor for l1. the recommended shielded inductor is available from coilcraft: mss1278t-154. please refer to: http://www.coilcraft.com/pdfs/mss1278t.pdf.
si3460-evb 10 rev. 1.1 6.7. r43 and r47 resistors r43 and r47 together dissipate about 1 w of po wer during normal operation. resistors r43, r47, and r44 (127 ? ) are chosen based on the ieee mi nimum disconnect curr ent specifications and to ensure good transient response for sudden load changes. to help ensure that heat dissipated by r43 and r47 does not unduly contribute to the heating of the pcb, it is recommended to move these resistors away from other heat-dissipating components, such as switching fet m1, inductor l1, and switching diode d8.
si3460-evb rev. 1.1 11 7. output voltage and load current waveforms figures 4 through 9 show output voltage and load current waveforms during startup and fault conditions. see the si3460-evb schematics in figures 10 and 11. figure 4. waveform showing detection pulse into open-circuit figure 5. output voltage waveform showing both detection and classification pulse during startup ch1: output voltage (v out+ ) ch1: output voltage (v out+ )
si3460-evb 12 rev. 1.1 figure 6. waveforms showing successful powerup figure 7. disconnect waveforms with time delay of 350 ms ch1: output voltage (v out+ ) load = 25 k ? ch1: output voltage (v out+ ) ch2: load current i out+ (v out+ )
si3460-evb rev. 1.1 13 figure 8. waveform showing overcurrent disconnect delay time of 60 ms figure 9. overcurrent during startup with 400 ma overload ch1: output voltage (v out+ ) ch2: load current i out+ (v out+ ) ch1: output voltage (v out+ ) ch2: load current i out+ (v out+ )
si3460-evb 14 rev. 1.1 8. si3460-evb schema tics and pcb layout full schematics and layout information are provided in the following sections. to ensure you are using the latest schematic and pcb layout database re visions, download the following zip file from the silicon laboratories si3460 documentation page: http://www.silabs.com/products/power/poe /pages/powersourcingequipment.aspx 8.1. schematics 0 drain deta dc1 250k drain vdd vee vdd dc2 pwm 0.5w 0.3v 1w 1w schottky 0.5w place both near mcu vout(+) vout(-) vin (-) vin (+) reset common mode chokes for gbe midspan m1 fqd12p10 m1 fqd12p10 c19 47u c19 47u r44 127 r44 127 r31 np r31 np r5 499 r5 499 u3 mic4417 u3 mic4417 gnd 1 out 2 vcc 3 ctl 4 c8 0.1u c8 0.1u c20 68u 35v c20 68u 35v u19a lm319 u19a lm319 out 12 + 4 - 5 g 3 v+ 11 v- 6 c21 0.1u /50v c21 0.1u /50v l3b fa2536-ald l3b fa2536-ald 6 5 4 r45 20k r45 20k c12 10n c12 10n c1 0.1u c1 0.1u r41 18.2k r41 18.2k r18 100k r18 100k d12 smaj58a d12 smaj58a r30 2k r30 2k c15 0.1u c15 0.1u c4 0.1u c4 0.1u d13 551-0207 d13 551-0207 r40 332 r40 332 r4 2.49 r4 2.49 c17 0.1u c17 0.1u q12 bc856 q12 bc856 u2 si3460 u2 si3460 gate 1 ctrl1 2 ctrl2 4 250khz 5 deta 6 vsense 7 isense 9 status 10 rst 8 vdd 3 gnd 11 r7 40.2k r7 40.2k j8 rj45 j8 rj45 3 1 4 2 5 6 7 8 d8 b2100 d8 b2100 r8 66.5k r8 66.5k r22 1k r22 1k c7 0.1u c7 0.1u u1 tlv431 u1 tlv431 l3a fa2536-ald l3a fa2536-ald 1 2 3 c3 1u c3 1u r43 1.3k r43 1.3k c16 1u c16 1u c13 0.1u c13 0.1u r24 1k r24 1k m2 fqt5p10 m2 fqt5p10 c9 0.1u c9 0.1u s1 0 s1 0 r42 1.82k r42 1.82k r28 np r28 np l5 330ohms l5 330ohms 1 2 c11 27n c11 27n c2 10u c2 10u l1 150uh l1 150uh 1 2 r47 1.3k r47 1.3k j7 rj45 j7 rj45 3 1 4 2 5 6 7 8 c18 0.1u c18 0.1u l2 4.7uh l2 4.7uh 1 2 c14 1u c14 1u j4 conn jack pwr j4 conn jack pwr 3 2 1 r27 10.5 r27 10.5 figure 10. si3460 and power circuit
si3460-evb rev. 1.1 15 0 0 0 deta dc2 dc1 250k vdd vee pwm drain r1 10k r1 10k r10 1meg r10 1meg r2 24.9k r2 24.9k r12 1meg r12 1meg r21 5.9k r21 5.9k r15 549k r15 549k r19 10k r19 10k r3 10k r3 10k r29 2.15k r29 2.15k r26 10k r26 10k r49 53.6k r49 53.6k r20 10k r20 10k r11 10k r11 10k u19b lm319 u19b lm319 out 7 + 9 - 10 g 8 v+ 11 v- 6 r16 324k r16 324k c10 470pf c10 470pf c22 0.1u c22 0.1u r48 53.6k r48 53.6k c5 0.015u c5 0.015u r6 1.40meg r6 1.40meg u18a lm2904 u18a lm2904 + 3 - 2 v+ 8 v- 4 out 1 r13 301k r13 301k r17 100k r17 100k r14 2k r14 2k r9 383k r9 383k r46 2k r46 2k u18b lm2904 u18b lm2904 + 5 - 6 v+ 8 v- 4 out 7 figure 11. detection and pwm circuit
si3460-evb 16 rev. 1.1 8.2. pcb layout figure 12. top side component placement figure 13. top side interconnect
si3460-evb rev. 1.1 17 figure 14. si3460 ground plane figure 15. si3460 power plane
si3460-evb 18 rev. 1.1 figure 16. bottom side interconnect
si3460-evb rev. 1.1 19 9. bom component considerations see section ?10. bill of materials?. to achieve optimal performanc e and full specification complia nce, silicon labs strongly encourages the use of the components and vendor part numbers listed in the bom. if alternate components must be substituted, please note the following recommendations for components in the power section. ? the digital control loop for the dc -dc converter has been optimized for stability with the ~41 f total output capacitance and 150 h shielded inductor (l1). capacitors c19, c20, c3, and c14 must provide suitably low esr for ripple considerations. ? diode d8 must have su itable high voltage and low recovery time. a schottky diode works well. ? diode d12 must not clamp at 57 v and must clam p to <100 v under worst case surge conditions. ? transistors m1 and m2 are sized for overall efficiency. the larger fqd8p10 can be used in both places, if desired. ? the fet gate driver should be capable of sinking and sourcing approximately 2 a. ? heat dissipating components must be separated from eac h other and moved away from components that are heat-sensitive. an example would be moving heat-dissipating inductor l1 so that it is kept away from electrolytic capacitors c19 and c20. ? for better electromagnetic interference (emi) performanc e, high current carrying inductors must be of the shielded type. other component considerations: ? resistors r23, r25 and the programming header j6 are used for development purposes only. the si3460 is not user programmable, and it is not recommended thes e components be included in actual layouts (short r23 and r25, and remove j6).
si3460-evb 20 rev. 1.1 10. bill of materials table 4. si3460-evb bill of materials qty ref value rating tol dielectric pcb footprint mfr part # mfr external pse bom (r-bom) 4c1,c7, c8, c21, c22 0.1 f 100 v 10% x7r 603 c0603x7r101104k venkel or equiv. 1 c16 1 f 10 v 10% x7r 603 c0603x7r100106k venkel or equiv. 1 c2 10 f 6.3 v 10% x5r 603 c0603x5r6r3106k venkel or equiv. or murata 1 c11 27 nf 100 v 10% x7r 603 c0603x7r101273k venkel or equiv. 1 c12 10 nf 100 v 10% x7r 603 c0603x7r101103k venkel or equiv. 1 c20 68 f 25 v 20% al elec 10mm eeefc1e680p panasonic or equiv. 1 d12 smaj58a 58 v sma diodes inc or equiv. 1 m2 fqt5p10 100 v sot-223 fqt5p10 diodes inc or equiv. 1 q12 bc856 sot23 bc856a diodes inc or equiv. 3 r1,r11, r26 10 k ? 1% rc0603 cr0603-10w-1002f venkel or equiv. 1 r2 24.9 k ? 1% rc0603 cr0603-10w-1002f venkel or equiv. 1r3 10k ? 1% rc0805 cr0805-8w-1002f venkel or equiv. 1r4 2.49 ? 1% rc1210-2w cr1210-2w-2r49f venkel or equiv. 1r5 499 ? 1% rc1210-2w cr1210-2w-4990f venkel or equiv. 1r61.40m ? 1% rc0603 cr0603-10w-1404f venkel or equiv. 1 r7 40.2 k ? 1% rc0603 cr0603-10w-4022f venkel or equiv. 1 r8 66.5 k ? 1% rc0603 cr0603-10w-6652f venkel or equiv. 1 r9 383 k ? 1% rc0603 cr0603-10w-3833f venkel or equiv. 2 r10,r12 1 m ? 1% rc0805 cr0805-10w-1004f venkel or equiv. 2 r13 301 k ? 1% rc0603 cr0603-10w-3013f venkel or equiv. 1 r31 np 1% rc0603 np venkel or equiv 1 r16 324 k ? 1% rc0603 cr0603-10w-3243f venkel or equiv. 2 r17,r18 100 k ? 1% rc0603 cr0603-10w-1003f venkel or equiv. 1 r21 5.90 k ? 1% rc0603 cr0603-10w-5901f venkel or equiv. 0 r28 np - see table 1% rc0603 see table venkel or equiv.
si3460-evb rev. 1.1 21 1r302k ? - see table 1% rc0603 cr0603-10w-2001f venkel or equiv. 2 r22,r24 1 k ? 1% rc0603 cr0603-10w-1001f venkel or equiv. 1r40 332 ? 1% rc0603 cr0603-10w-3320f venkel or equiv. 1r44 127 ? 1% rc0603 cr0603-10w-1270f venkel or equiv. 1 r41 18.2 k ? 1% rc0603 cr0603-10w-1822f venkel or equiv. 1 r42 1.82 k ? 1% rc0603 cr0603-10w-1821f venkel or equiv. 1 r45 20 k ? k 1% rc0603 cr0603-10w-2002f venkel or equiv. 2 r48,r49 53.6 k ? 1% rc0603 cr0603-10w-5362f venkel or equiv. 1 u1 tlv431 sot23 tlv431 on semi or equiv. 1 u18 lm2904 so8 lm2904 on, fairchild or equiv. step-up dc/dc converter (r-bom) 2 c3,c14 1 f 100 v 10% x7r 1210 c1210x7r101105k venkel or equiv. 2 c4, c9 0.1 f 100 v 10% x7r 603 c0603x7r101104k venkel or equiv. 1 c5 0.015 f 16 v 10% x7r 603 c0603x7r160153k venkel 1 c10 470 pf 100 v 10% x7r 603 c0603x7r101471k venkel or equiv. 1 c19 47 f 100 v 20% al elec 12.5mm eevfk2a470q panasonic 1 d8 b2100 100 v schottky smb b2100 diodes inc 1 l1 150 h 2 a do3340 mss1278t-154kld coilcraft 1 l2 4.7 h lps3314 lps3314-472ml coilcraft 1 m1 fqd12p10 100 v to252 (d-pak) fqd12p10 fairchild 2 r14,r46 2 k ? 1% rc0603 cr0603-10w-2001f venkel or equiv. 1 r15 549 k ? 1% rc0603 cr0603-10w-5493f venkel or equiv. 2r19, r20 10k ? 1% rc0603 cr0603-10w-1002f venkel or equiv. 1r27 10.5 ? 1% rc0603 cr0603-16w-10r5ft venkel or equiv. 1 r29 2.15 k ? 1% rc0603 cr0603-10w-2151f venkel or equiv. 1r43, r47 1.3k ? 5% rc2512-1w cr2512-1w-132jt venkel 1 u3 mic4417 sot143-4 mic4417 micrel or equiv. 1 u19 lm319 so14 lm319 st, fairchild or equiv. table 4. si3460-evb bill of materials (continued) qty ref value rating tol dielectric pcb footprint mfr part # mfr
si3460-evb 22 rev. 1.1 si3460 pse controller, gbe common mode chokes, status led, and other optional components 1 u2 si3460 pse + pwm dc-dc controller 3x3 mm 11-p qfn si3460 silicon labs 1 d13 551-0207 led 100 right angle 551-0207 dailight or equiv. 1 j4 jack pwr 2.1id 5. 5od 16pj031 kobiconn 2 j7,j8 rj45 pcb 8/8 95001-2881 molex 1 l3a,b fa2536 gbe chokes fa2536 fa2536-al coilcraft 1 l5 330 ? 1.5 a 25% ferrite bead 805 blm21pg331sn1d murata 4 c13,c15, c17,c18 0.1 f 250 v 0.1 for chokes 1210 c1210x7r251104k venkel or equiv. 1 s1 sw_topen mouser 101-0161 1power supply 12 v 1.5 a dps120150u-p5p cui inc bom alternates 1power supply 12 v 2.5 a ems120150-p5p-sz cui inc dms120250-p5p-ic cui inc 1 c19 39 f 100 v 20% al elec 10 mm eeufc2a390l panasonic 1 u3 tps2828 sot-23 5pin tps2828 ti notes: 1. r28 and r30 indicate the classification level. full power midspan configuration is (r28 np) (r30 = 2 k ?? . 2. although v1.3a evbs are shipped with a non-shielded inductor, shielded inductor l1 is strongly recommended for emi performance considerations (see ww w.coilcraft.com/pdfs/mss1278t.pdf). 3. the capacitor is radial-leaded and can be used if the height restriction is not an issue. table 4. si3460-evb bill of materials (continued) qty ref value rating tol dielectric pcb footprint mfr part # mfr
si3460-evb rev. 1.1 23 11. operating the si3460-evb the si3460-evb itself is very simple to use. only a basic 12 or 15 v dc power source (i.e., a wall wart) with at least an 18 w rating is needed fo r connection to j4. the si346 0 will automatically power up , detect the operational modes (midspan/endpoint, classification power level, and restart mode), and then begin the detection process, during which the led flashes at 3 times per second. figure 17. si3460-evb to test the si3460-evb in a poe environment, many co mmercial pds are available, such as wireless access points (waps), voice over ip phones (voip), and ip-based security cameras. any of t hese can be connected to the si3460-evb to receive pse power while exchanging et hernet traffic. another pd option is to use the si 3460-evb with one of the si3400/01 evalua tion boards. if a si3400 evb is used with the si3460-evb, the s3400 evb should be configured to present a minimum load of > 0.25 w to ensure that it draws at least 10 ma to comply with the ieee standard. when the si3460 is applying power to a valid pd, the le d is continuously lit. after an error condition (e.g., an uvlo or short-circuit event) is detected, the led flashes at 10 times per second, or until a reset is asserted, or when an open circuit is detected as determ ined by the operating mode of the si3460. resistors r23, r25, and the programming header j6 are used for development purposes only. the si3460 is not user programmable, and it is not recommended these components be included in actual layouts (short r23 and r25, and remove j6). the si3460 mode is set by resistors r28 and r30. placeholder values of 10 k ? are shown in the schematics. to keep the voltage level at the transistor base accurate, it is recommended that the pa rallel resistor combination setting the pin voltage be less than 2 k ? . it is expected that most applicati ons will support full power in either a midspan or endpoint application and enable automatic reset after an overload. the reference board is shipped configured for midspan power injection with full power support and automatic retry after a fault. resistors r28 and r30 may be replaced to support other modes of operation. see section "5.1. initialization and operating mode configuration" on page 5 for more information.
si3460-evb 24 rev. 1.1 12. summary with its integrated dc-dc converter and fully compliant pse interface, the si3460- evb provides a simple and comprehensive applications solution for pse systems des igners who require ieee-c ompliant pse functionality and safe operation with standard telephone interfaces and voltages. 13. ordering guide ordering part number description si3460-evb evaluation board for si3460 si ngle-port pse controller fo r embedded applications. si3460-xyy-gm refer to the si3460 data sheet ordering guide section for more information.
si3460-evb rev. 1.1 25 d ocument c hange l ist revision 0.1 to revision 0.2 ? updated figure 17, ?si3 460-evb,? on page 23. ? revised document formatting throughout. revision 0.2 to revision 0.3 ? added figures 4 through 9. ? updated "2. overview of the si3460 and evaluation board" on page 1. ? updated "4.3. power-up" on page 4. ? updated "4.4. disconnect (power removal)" on page 4. ? updated "5.3. detect ion" on page 6. ? updated "5.5. classific ation" on page 6. ? updated "5.6. power-up" on page 7. ? updated "5.7. disconnect (power removal)" on page 7. ? updated "5.8. current limit control" on page 7. ? updated "5.9. uvlo" on page 7. ? updated "6.2. isolation" on page 9. ? added "7. output voltage and load current waveforms" on page 11. ? updated title of figure 9 on page 13. ? updated figure 17 on page 23. ? reformatted "10. bill of materials" on page 20. ? updated schematics, pcb layouts, and bom. revision 0.3 to revision 1.0 ? updated table 3 on page 6. ? updated "5.6. power-up" on page 7. ? updated "5.8. current limit control" on page 7. ? updated "5.10. status led function" on page 8. ? updated "6.5. emi and emc" on page 9. ? updated schematics. ?? removed r31. ? updated "10. bill of materials" on page 20. revision 1.0 to revision 1.1 ? updated "6.5. emi and emc" on page 9. ? updated "8. si3460-evb schematics and pcb layout" on page 14. ? updated figure 10, ?si3460 and power circuit,? on page 14. ? updated figure 11, ?detection and pwm circuit,? on page 15. ? updated figure 12, ?top side component placement,? on page 16. ? updated figure 13, ?top side interconnect,? on page 16. ? updated figure 14, ?si3460 ground plane,? on page 17. ? updated figure 15, ?si3460 power plane,? on page 17. ? updated figure 16, ?bottom side interconnect,? on page 18. ? updated "9. bom component considerations" on page 19. ? updated "10. bill of ma terials" on page 20. ? updated "11. operating the si3460-evb" on page 23.
si3460-evb 26 rev. 1.1 c ontact i nformation silicon laboratories inc. 400 west cesar chavez austin, tx 78701 tel: 1+(512) 416-8500 fax: 1+(512) 416-9669 toll free: 1+(877) 444-3032 email: poeinfo@silabs.com internet: www.silabs.com silicon laboratories and silicon labs are trademarks of silicon laboratories inc. other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. the information in this document is believed to be accurate in all respects at the time of publ ication but is subject to change without notice. silicon laboratories assumes no responsibility for errors and om issions, and disclaims responsibi lity for any consequences resu lting from the use of information included herein. ad ditionally, silicon laboratorie s assumes no responsibility for the functioning of und escribed features or parameters. silicon laboratories reserves the right to make changes without further notice . silicon laboratories makes no wa rranty, rep- resentation or guarantee regarding the suitability of its products for any particular purpose, nor does silicon laboratories as sume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including wi thout limitation conse- quential or incidental damages. silicon laborat ories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of t he silicon laboratories product could create a s ituation where per- sonal injury or death may occur. should buyer purchase or us e silicon laboratories products for any such unintended or unauthor ized ap- plication, buyer shall indemnify and hold silicon laboratories harmles s against all claims and damages.

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